Chips may be arranged regularly together in panel form or wafer form, e.g. in a reconstituted wafer form, in a chip package formation such as in embedded wafer level ball grid array (eWLB). A metal layer, which may be designated as a redistribution layer (RDL), may serve as an electrical connection to external connection pads. An embedded wafer level package, e.g. embedded wafer level ball grid array (eWLB) may have several associated problems, significant parts of which may be attributed to the mold compound. Problems may include warpage, deformation, e.g. x-y deformation, outgassing from the material, problems with the temperature cycling on board (TCoB) cycling durability, poor thermal conductivity, and difficulties associated with contacts, e.g. backside of the ICs leads to contact.